IBM Research says a team of agents using open GLM-5.3 models reduced the estimated processing time of one quantum-error-correction decoder from 28,231 microseconds to 545 microseconds. The estimate came from high-level synthesis, and the model inference for that search run was estimated at $25.95. The result compares one 100-hypothesis search on a specific FPGA design; it is not a measurement of a fabricated chip.
Agents searched variations of a quantum decoder
The experiment focused on a Relay-BP decoder for a [[144,12,12]] bivariate-bicycle quantum error-correction code. A decoder estimates which errors likely occurred from measurements made during error correction. IBM's “agent factory” assigned different roles to AI agents: a coordinator proposed and organized candidate design changes, while worker agents explored them in parallel. The system checked candidate C/C++ designs and used Vitis high-level synthesis (HLS) to estimate how they would map to a Xilinx VU19P FPGA.
HLS translates high-level code into a hardware design and estimates its properties before a chip is built. The agents used those results to guide later proposals. IBM reports the best feasible design found in each search, rather than the average performance of all generated candidates.
Open models cost less; the proprietary setup was faster
With GLM-5.3 in both coordinator and worker roles, served on premises through llm-d, the system found a design with an estimated latency of 545 microseconds, about 52 times faster than the 28,231-microsecond reference. IBM estimated the model inference at $25.95 and reported 78 feasible designs in the 100-hypothesis search.
A hybrid setup using Claude Opus 5 as coordinator and GLM-5.3 as workers reached 223 microseconds, a reported 126-fold speedup, at an estimated $105.25 in inference cost; it produced 85 feasible designs. Using Opus 5 for both roles reached 139 microseconds, or 204 times the reference speed, for $299.45 and 63 feasible designs. The comparison shows a speed-cost tradeoff in this task: the all-open setup was the least expensive, while the all-Opus setup found the fastest design.
In a separate scaling test, IBM extended the GLM-5.3 coordinator-and-worker search from 100 to 200 hypotheses. Its best HLS-estimated latency improved from 544.7 microseconds, 51.8 times faster than the reference, to 467.6 microseconds, 60.4 times faster. The paper says the added search brought diminishing returns: the second 100 hypotheses improved latency by a further 1.16 times.
The figures stop at an estimated design
These numbers describe one search run per model configuration, on one decoder and one FPGA target. HLS latency is a synthesis estimate, not a timing measurement from fabricated or deployed hardware. The reported dollar amounts cover model inference, not the full cost of chip design, synthesis, validation or engineering. The experiment therefore demonstrates a bounded design-space search; it does not establish a general ranking of AI models or show that a quantum computer used this decoder.
Image: Photo by Thotypous (Paulo Matias), CC BY-SA 3.0, via Wikimedia Commons. Illustrative FPGA board, not the hardware tested in IBM's study. Image details.
