IBM and Siemens say they will develop design, simulation and lithography methods for IBM's 3D nanostack transistor architecture, a technology the companies hope to prepare for future manufacturing. Their Oct. 14 announcement describes work on virtual models to test designs and fabrication challenges before chips are built.
The collaboration follows IBM's June demonstration of a 0.7-nanometer, or 7-angstrom, chip design. IBM says that design stacks and offsets nanosheet transistors vertically, allowing more devices in the same footprint. IBM reported nearly 100 billion transistors on a 150-square-millimeter chip and said the research showed 40% scaling in SRAM, a type of on-chip memory. Those are IBM's research results; the October partnership release gives no new silicon measurements.
IBM and Siemens plan to work on the tools that let chip designers and process engineers test the architecture. The announced areas include electronic design automation, process simulation, lithography optimization and advanced manufacturing software. Virtual models could let teams explore performance and design constraints before committing to physical chip builds, but the companies have not yet reported results from this work.
A day earlier, IBM Research said it plans to make an early research-and-development process design kit for the 7-angstrom technology available in the first quarter of 2027. A process design kit gives chip designers a set of rules and models for exploring circuits that fit a particular manufacturing process. IBM describes this one as an early R&D resource; its announcement does not say that the process will be ready for commercial production then.
The two updates describe development steps between a transistor demonstration and manufacturable chips: tool development and an early R&D kit that could help researchers test layouts. Denser logic and memory may help future AI hardware, but the announcements do not show a commercial chip or a measured performance gain.
Sources
- IBM and Siemens Collaborate on Research to Advance Nanostack Architecture (Oct. 14, 2026)
- Preparing chip designers for the nanostack era (Oct. 13, 2026)
- Introducing the first sub-1 nanometer node chip (June 25, 2026)