A quantized neural accelerator called LP-YOLO Slim met its project's four targets for vehicle detection on a PYNQ-Z1 board: real-time throughput, energy efficiency, programmable-logic latency and Pascal VOC accuracy. The result came from treating the detector and the small FPGA as one design problem rather than optimizing the neural network alone.
The PYNQ-Z1 combines an Arm processor with programmable logic in a Xilinx Zynq-7020 system-on-chip. In the researchers' design, the FPGA fabric runs the detector's quantized convolutional layers as a streaming pipeline. The Arm side handles transfers, control, output decoding and non-maximum suppression, which removes overlapping detections.
The project set four explicit thresholds before selecting a final design: more than 30 frames per second, more than 7 frames per second per watt, less than 50 milliseconds of latency inside the programmable logic, and more than 0.55 mean average precision at an intersection-over-union threshold of 0.5 on Pascal VOC. Mean average precision summarizes how well the detector finds and localizes the requested object classes.
Model compression and hardware tuning had to work together
The team trained lightweight YOLO-derived detectors with quantization-aware training, which exposes the model to low-precision arithmetic during training. Brevitas exported the trained network as a quantized QONNX graph. AMD's open-source FINN toolchain then turned the graph into a dataflow accelerator, applying layer parallelism, folding and FIFO sizing before Vivado generated the FPGA bitstream.
The final LP-YOLO Slim configuration used 256 by 256 pixel inputs, two-bit internal weights and four-bit activations. At a 125 MHz programmable-logic clock it already reached 31.22 frames per second, 11.15 frames per second per watt and 0.594 VOC mAP@0.5. Its measured hardware latency was 51.49 milliseconds, however, missing the latency target by 1.49 milliseconds.
Keeping the model fixed and raising the clock to 142.86 MHz moved the same design across that boundary. With batches of 100 images, the board delivered 35.66 frames per second at 2.91 watts, or 12.25 frames per second per watt. Programmable-logic latency fell to 45.11 milliseconds while the reported VOC score remained 0.594. It was the only evaluated configuration for which the paper supplied measurements that cleared all four gates together.
Balancing accuracy, speed and power
A larger custom YOLOv3-tiny model reached 0.761 VOC mAP@0.5, but ran at 12.35 frames per second with 94.87 milliseconds of hardware latency and 5.94 frames per second per watt. A faster LP-YOLO build with automatically sized FIFOs reached 35 frames per second and 16.28 frames per second per watt, but its VOC score was 0.39. The Slim model occupied the usable middle: less accurate than the larger detector, yet small enough to satisfy the board-level limits.
The reported latency is specifically the FPGA portion of the system. Some configurations also include end-to-end measurements that cover Arm-side processing and transfers, so the two columns should not be treated as interchangeable. Accuracy coverage is uneven as well. The authors did not supply mAP for every clock and FIFO experiment, which is why those rows cannot be called four-target solutions even when their speed and power numbers look stronger.
The paper also reports 0.492 mAP@0.5 for the Slim model on a filtered COCO-derived evaluation, but that number is not directly comparable with the 0.594 VOC result. The corpora differ, and the authors measured substantially smaller vehicle boxes in the COCO-derived set. The study uses VOC as its stated closure test and explicitly warns against merging the two evaluations.
The study includes physical power and latency measurements on one small Zynq board. It does not establish performance on other FPGA families, camera pipelines or road conditions.
Sources
- Paper record and abstract, submitted September 21, 2026
- Full paper with design, measurements and limitations
- Representative FPGA development board image by Popolon, CC BY-SA 4.0
- Lead image: a representative Sipeed Tang Nano 4K FPGA development board, not the PYNQ-Z1 used in the study.