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Memristor Chip Runs Singular Value Decomposition in Memory

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Illustrative close-up of a carbon memristor memory device photographed by the U.S. Department of Energy

A 130-nanometer memristor chip has executed singular value decomposition inside memory, reducing the need to move numbers between storage and a processor. A separate gesture-recognition test, combining measured device behavior with simulated peripheral circuits, stayed close to software accuracy.

Singular value decomposition, or SVD, breaks a matrix, a table of numbers, into ranked components. Those components support compression, denoising, feature extraction and low-rank model updates. Conventional processors repeatedly move the matrix and intermediate results between memory and computing units. The system reported in Nature Communications instead stores each value as electrical conductance, how easily a memory cell carries current, so the array can multiply numbers where the data already reside.

That physical shortcut creates an accuracy problem. The algorithm finds a dominant component, subtracts its contribution and then looks for the next one. Errors in the stored numbers can grow over repeated calculations or leave part of the old component behind. The researchers store the most consequential bits in more robust states while preserving finer detail separately. For the subtraction step, they increase input precision and average outputs from repeated copies of the solved vectors, reducing noise without duplicating every matrix. A 1,024 by 128 array works with programmable logic and CPU control around the analog operations.

The gesture test used electrical muscle recordings from ten channels to distinguish four hand movements. It combined measured memristor behavior with simulated larger peripheral circuits; it was not a complete gesture-recognition pipeline running solely on the chip. For two users, this hybrid system averaged 88.26 percent accuracy across 15 repeats, compared with 89.58 percent for the software calculation. When the dataset expanded from two to eight users, updating the stored decomposition produced 84.01 percent average accuracy; reusing the original two-user vectors without an update produced 64.72 percent. These are comparisons inside the paper's own recognition pipeline, rather than a general benchmark against other chips.

The energy and speed figures require a separate reading. A modeled 32-nanometer system consumed 13.40 microjoules for one decomposition, while the authors estimated 400 microjoules for an Nvidia A100 on the same operation count. Their area-normalized speed estimate was 19.0 times the A100 figure. The fabricated device is a 130-nanometer chip, and the paper estimates a smaller 10-fold energy advantage at that node. Large-scale tests, including LLaMA 3.2 weight initialization, used simulations calibrated with measured device noise because the physical array was too small.

The work establishes that iterative SVD can survive real memristor variation when precision is assigned around the algorithm's failure points. It does not yet show a full model decomposition running on a production-size array or measured wall-plug efficiency for an integrated product.

Correction (22 September 2026): The gesture-recognition result combined measured memristor behavior with simulated larger peripheral circuits. An earlier version described it simply as a hardware experiment without making this hybrid setup clear.

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