Researchers have used a magnetic-memory chip to test a different way of choosing wire routes and layers inside computer chips. The device represents possible choices as 96,000 interacting binary “spins” that can switch with adjustable probability. The peer-reviewed study appeared September 22 in Nature Electronics.
An Ising machine searches for a combination of linked choices that scores well under an optimization rule. In this version, each spin is a cell in magnetoresistive random-access memory integrated with conventional chip circuitry. Changing the width of a voltage pulse tunes the chance that a cell flips, letting the system explore different solutions. The researchers applied it to global routing and layer assignment, two stages of connecting a chip's components.
The team reports spin updates in 0.3 to 1 nanosecond and less than 40 femtojoules of energy per spin. On a separate Max-cut benchmark, the system delivered about 192,000 solutions per second per watt. That whole-system benchmark does not measure the speed of a complete chip-routing workflow.
Sources
- Li et al., “An Ising machine for combinatorial optimization based on sub-nanosecond CMOS-integrated magnetoresistive random-access memory,” Nature Electronics (September 22, 2026)
- Earlier preprint, posted January 23, 2026
- Illustrative photograph of an earlier MRAM die, not the study chip: Steve Jurvetson, Wikimedia Commons, licensed under CC BY 2.0.
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