Researchers used a language model to help a formal verifier complete two hardware security checks that had timed out after 12 hours. In a paper posted September 22, their method proved that selected public outputs stayed independent of protected inputs under the tests' stated assumptions. A conventional solver, rather than the model, decided whether each proof was valid.
To test whether secret data can affect an observable output, engineers can run two virtual copies of a circuit with the same public inputs but different protected values. If the outputs always agree, the chosen output does not reveal that source under the specified conditions. Complex arithmetic and control logic can make that two-copy proof hard to finish.
The model proposes a shorter route to the proof
The system, called SLED-IFV, uses Claude Opus 4.7 to choose between two ways through the problem. For a difficult calculation, the model can propose a simpler description of a circuit region's behavior; the solver must prove that description holds for the real design. For a control problem, it can propose relationships between the two copies' public control states, which the solver must prove alongside the original security property.
A controller checks the generated proof files before submitting them. It rejects changes to the original property or assumptions, and runs deliberately false and leaky controls to catch a proof setup that could pass for the wrong reason. Failed proposals go back to the model with the solver's feedback.
Two 12-hour timeouts became completed proofs
The researchers tested nine difficult information-flow questions built from public hardware designs and masking components, using the same ABC-PDR proof engine for the baseline and their method. The baseline timed out at 12 hours on an Ibex processor memory-access test and a masked mini-cipher test. SLED-IFV completed the solver checks in 55.8 seconds and 13.8 seconds, respectively. The strongest reported speedup on a completed baseline was about 603 times for an OpenTitan-derived security arithmetic case.
Those speedups count solver work, not the whole model-guided process. Each round of model proposals and proof-file generation took about 25 seconds on average, and the system typically needed one to four rounds. Solver feedback also mattered: three first attempts chose the wrong target, while the repair loop raised accepted results from six of nine cases to nine of nine. Each result covers the specified source, output and assumptions of a benchmark question; the study does not establish security for an entire chip.
Sources
- Dai and colleagues, “SLED-IFV: Solver-Validated LLM-Guided Decomposition for Scalable Hardware Information-Flow Verification”, arXiv, September 22, 2026.
- Full research paper and benchmark tables, arXiv PDF.
- Illustrative image: integrated circuit photograph by Jon Sullivan, public domain / CC0. The image does not depict the research team's test hardware.
