On Sept. 22, IonQ publicized an August preprint showing its decoder added 0.02% to 0.72% to the schedule of a 408-logical-qubit workload in simulation. The test used a MacBook CPU, not a quantum processor.
Quantum computers detect errors through repeated measurements that reveal information about a computation without directly reading its encoded data. A classical decoder must interpret those measurements quickly enough to keep work moving. If it falls behind, the processor can need extra error-checking cycles before a later logical measurement finishes.
The study by IonQ researchers Min Ye, Andrii Maksymov and Nicolas Delfosse models the company’s proposed Walking Cat architecture. A logical qubit is an error-protected information unit encoded across multiple physical qubits. The largest workload held 408 logical qubits in 68 Q70 memory blocks, with six logical qubits encoded in each; 20 additional CH2 magic-state factories brought the model to 88 blocks and 11,680 physical qubits.
In this architecture, blocks stream repeated syndrome-extraction cycles, the measurements used to detect errors. Logical measurements add temporary cat-state measurements, which use entangled auxiliary qubits. Two decoders split the work: one continuously updates a software record of likely Pauli errors, called a frame; the other runs only for logical measurements and uses a shorter window to return their outcomes sooner. Those outcomes can determine the next operation, so the split helps keep that decision from waiting on the continuous decoder.
The software also reuses a fixed map linking possible faults to measurement patterns. When a cat-state measurement enters a decoding window, it updates the affected error probabilities on that map; when the measurement leaves, it restores the ordinary-memory probabilities instead of rebuilding the graph. Memory optimizations to the beam-search decoder reduced its footprint by more than an order of magnitude, the paper reports. That let 12 decoder processes share the same CPU.
The largest benchmark simulated a disordered Heisenberg model on 266 sites and included more than 1.3 million logical measurements. The decoder ran on a 2024 MacBook Pro with an M4 Max chip, using 12 of its 16 CPU cores: eight for continuous error decoding and four for measurement outcomes.
All results came from a circuit-level noise model, not measured processor data. The researchers tested two-qubit gate error probabilities from 0.01% to 0.05%, a range the paper says has been achieved on small trapped-ion devices. They assumed a five-millisecond error-check cycle for the 408-qubit case; the two 102-qubit tests used one millisecond.
For the largest workload, added schedule time, or “stretch,” ranged from 0.02% at the lowest modeled error rate to 0.72% at the highest. Stretch is the additional error-check cycles divided by the number of cycles in the schedule with zero decoder delay. At the highest modeled error rate, stretch was 10.25% to 11.53% in the smaller tests. Because those workloads used a shorter cycle-time budget, the figures are not a like-for-like scale comparison.
The paper also reports rare decoder-convergence failures, which are different from ordinary delays and can require restarting a computation. In the factory simulation, the authors substituted a stabilizer state for the physical magic state so they could benchmark decoder workload rather than factory output fidelity. The results show that one CPU can meet the timing assumptions for these simulated workloads; they do not establish performance in a feedback loop with an operating quantum processor or the fidelity of a completed computation. A closed-loop test with measured processor data remains the practical next check.
Sources
- Min Ye, Andrii Maksymov and Nicolas Delfosse, “Real-time decoder for a MegaQuOp quantum computer using a single CPU,” arXiv:2608.25027 (first submitted Aug. 25; revised Sept. 3, 2026).
- IonQ, Sept. 22 announcement.
- Illustration: Bender2k14, three-qubit bit-flip error-correction circuit, CC BY 3.0, used unmodified. This is a general explanatory diagram, not the IonQ benchmark.
