Researchers at the Chinese University of Hong Kong, Zhejiang University and Shanghai Jiao Tong University have released FlashGPU-sim, an open-source program that models how recent Nvidia graphics processors execute AI workloads one instruction cycle at a time. In a paper submitted on September 14 and due to appear at MICRO 2026, the team reports a 5.24% average error in simulated cycle counts across 131 workload configurations on RTX 5090, H100 and B200 chips. The work gives academic hardware designers a public model for testing changes that cannot be made to a finished processor.
GPU simulators let engineers alter a software model of a processor and estimate how a workload would behave before new silicon exists. A cycle-accurate simulator attempts to reproduce when instructions, memory transfers and computing units become ready, rather than checking only whether a program returns the right answer. The comparison assembled by the researchers shows why an update is needed: widely used public Nvidia models extend to Volta, released in 2017, or Ampere, released in 2020. Recent AI kernels depend on asynchronous transfers and tensor-computing pipelines introduced in Hopper and Blackwell.
| Public simulator and latest architecture | Release year |
|---|---|
| gem5-gpu: Fermi | 2010 |
| Multi2Sim: Kepler | 2012 |
| GPGPU-Sim: Volta | 2017 |
| Accel-Sim: Ampere | 2020 |
| Huerta et al.: Ampere | 2020 |
| FlashGPU-sim: Blackwell | 2024 |
FlashGPU-sim starts by capturing a kernel written with Triton, a framework for creating custom GPU programs. Its TritonTrace tool records the compiled code, arguments and launch settings, then builds a standalone harness that can replay the kernel inside the simulator. During replay, the model tracks data moved by Nvidia's Tensor Memory Accelerator, the barriers that release waiting work and the tensor-core instructions that perform matrix calculations. Researchers can then change a modeled delay or resource and observe how the same program's timing changes.
The validation compared simulated cycle counts with measurements from Nvidia Nsight Compute on physical GPUs. The 131 configurations included matrix multiplication and FlashAttention kernels on an RTX 5090, FlashAttention-2 and FlashAttention-3 on H100, and FlashAttention-4 on B200. The team locked chip clocks for reproducible measurements. A separate speed test ran six inference matrix-multiplication workloads on an AMD EPYC host, with each simulation thread assigned to a physical CPU core.
Across those configurations, the mean absolute percentage error was 5.24%; this metric is the average absolute gap between simulated and measured cycle counts, expressed as a percentage. In the 55 RTX 5090 kernel configurations, 48 remained within 10% of the hardware measurement. Parallel execution also shortened the simulator's own running time by 7.86 times with 16 host threads, reducing a one-hour single-thread run to about 7.6 minutes in the authors' test.
The combination could make detailed GPU design experiments accessible to research groups without an internal chip simulator. The public repository still lists parts of the Blackwell model and distributed shared memory as work in progress, while multi-GPU and NVLink modelling remain planned. The paper therefore does not establish accuracy for complete multi-GPU systems or unbuilt processors. Independent reproductions, completion of the public roadmap and validation on larger end-to-end models are the next checks for researchers considering FlashGPU-sim for architecture decisions.
Related coverage
Sources
- Siying Yu and colleagues, “FlashGPU-sim: Enabling GPU Modeling for Modern Architectures and AI Workloads,” arXiv, September 14, 2026. Abstract, authorship, submission date, conference note and headline results.
- Full paper. Simulator design, public-tool comparison, validation conditions, results and stated future work. Lead photograph: Nick Stathas, CC BY-SA 4.0; the image is illustrative and does not show the GPUs used in the study.
- Official FlashGPU-Sim repository. Public code, supported configurations, workflow, dependencies and roadmap status.