Arteris introduced FlexGen Multi-Die on September 15, extending the circuitry that directs data inside a chip across connections between separate pieces of silicon. The new design technology aims to preserve traffic priorities as chipmakers divide AI computing systems into chiplets, smaller dies assembled within one package.
Inside a single die, a network-on-chip, or NoC, moves requests and data among processors, memory and accelerators. Splitting those functions across chiplets adds a physical crossing to that journey. Designers may use different manufacturing processes for different dies, but must also decide how traffic competes for the connections between them. A fast processor can still wait while its data is delayed at that boundary.
FlexGen Multi-Die adds a die-to-die controller to Arteris' existing network design technology. The controller packages the NoC's traffic into configurable transfer units called flits for transmission through a physical interface, or PHY. That interface carries electrical signals between dies. One supported interface standard is Universal Chiplet Interconnect Express, or UCIe. The consortium's specification covers physical connections, protocols and interoperability testing, providing a common framework for components from different suppliers.
Sharing that connection requires controls over competing flows. FlexGen's virtual channels let multiple logical traffic streams use the physical link while retaining separate flow control. Its quality-of-service mechanisms give priority to selected traffic, with the stated aim of maintaining its throughput when the link is shared. The company also says the design supports transactions in both directions over one UCIe physical interface. These are described capabilities; the announcement does not provide workload results showing how they behave under congestion.
The new product targets non-coherent systems, where this interconnect does not maintain a shared, automatically synchronized view of cached data across processors. Arteris offers Ncore Multi-Die for systems requiring that cache-coherent behavior. This distinction matters when choosing how separate compute dies exchange data: carrying a message and maintaining consistent cached copies are different requirements.
Availability is limited to early-access partners and strategic customers. The product page also marks its adapter layer for third-party physical interfaces as forthcoming, even while describing broad interface compatibility. Teams therefore need to check the particular controller-and-interface combination available to them. Arteris advertises design-time and efficiency improvements, but the public material reviewed does not supply enough matched test conditions to establish a general performance advantage over other chiplet interconnects.
For chip architects, the announcement adds an option for carrying existing NoC traffic controls into a design spread across dies. The next useful evidence would be a specified implementation showing whether priority traffic retains its throughput as competing traffic rises, together with the link's power cost and supported interfaces.